The present invention relates generally to input buffer circuits, and more particularly to an input buffer for converting low-level signals to higher-level signals.
In many modern semiconductor integrated circuits, there is a need to convert a low-level logic input signal to an output logic signal at a higher level. For example, it is often a requirement to convert a TTL input signal, which typically varies between 0 and 3.0 volts for a logic "0" and logic "1", to a higher-level CMOS swing which varies between 0 and 5 volts. In order for TTL circuits to be able to function with CMOS circuits, an interface or buffer must be provided between the two circuits to convert the relatively low TTL logic levels to higher levels at which CMOS circuits can reliably operate.
One relatively simple TTL to CMOS buffer is a CMOS inverter which receives a TTL-level input and provides a CMOS-level output. This TTL-CMOS inverter buffer includes an NMOS transistor, which is about five times wider than the PMOS transistor, in contrast to being half as wide as the PMOS transistor as is conventional in a typical CMOS inverter. Therefore, assuming a +5 volt supply, this CMOS inverter will typically switch its output through the entire CMOS range of 5 volts when its input passes through about 1.5 volts, rather than about 2.5 volts, the switching point in a normal CMOS inverter. More complex buffer circuits that perform this function are also known, as exemplified by the circuits described in U.S. Pat. Nos. 3,755,690 and 4,048,518.
A switching point of 1.5 volts for this inverter is suitable for operation with a TTL input, because the TTL convention is that a voltage level of 2.0 volts or greater is considered a logic "1" and a voltage level of 0.8 volts or less is considered a logic "0". However, these TTL 0.8 volt and 2.0 volt limits are a d.c. specification. TTL is normally operated under a.c. conditions with a swing of 0 to 3 volts, which places the 1.5 volts switching point of the simple buffer in the middle of the input TTL signal range.
If the input buffer has a switching point of 1.5 volts, and if the input is normally varying between 0 volts and 3 volts, the buffer is said to have a noise margin of about 1.5 volts on both sides of the switching point. That is, if the input is supposed to be at 0 volts, then almost up to a positive-going 1.5 volt short-duration noise pulse can be tolerated; thus, no error is introduced in the buffer output level if a noise pulse of this level appears at the input. Similarly, if the input is supposed to be at 3.0 volts, then a negative-going 1.5 volt noise pulse of only about 1.5 volts can be tolerated in this buffer. Therefore, both positive and negative-going pulses greater than 1.5 volts cannot be tolerated in this known input buffer, so that noise pulses at these levels cause an incorrect CMOS level to be produced in response to one or both of the TTL input levels.
It is an object of the present invention to provide an improved TTL to CMOS buffer with a higher noise margin, that is, one which can tolerate higher-level noise pulses.
The buffer of the invention is able to tolerate positive-going noise pulses of about 2.4 volts superimposed on an input of 0 volts, and can tolerate negative-going noise pulses of about 1.8 volts superimposed on an input of 3.0 volts. The buffer of the present invention satisfies the TTL d.c. specification of 0.8 volts for a logic "0" and 2.0 volts for a logic "1" The buffer of the invention meets these apparently contradictory goals by taking advantage of the fact that input noise is typically of short duration (a few nanoseconds to a few tens of nanoseconds), whereas the TTL d.c. specification input voltages are of a much longer duration.
The input buffer circuit of the present invention includes two separate paths between its input and output. The first is a high-speed a.c. path, which switches between the "0" and "1" logic states at a high switching voltage of about 2.5 volts on a rising 0 to 3 volt input signal, and switches between the "1" and "0" logic states at a low switching voltage of about 1.1 volts on a falling 3 to 0 volt input signal. The second path, which controls the operation of the first path, is a slower speed d.c. path, having a low switching voltage of about 1.1 volts, for both rising and falling input signals. By providing different a.c. and d.c. switching voltages, and by creating an hysteresis effect for the a.c. path the TTL to CMOS buffer of the invention is better able than conventional buffers to reject high-frequency input noise spikes.